1. Field of the Invention
This invention relates to a semiconductor device having a chip size package (CSP) structure and in particular to a chip size package improved in moisture resistance.
2. Description of the Related Art
To manufacture semiconductor devices, elements are built one after another in a wafer to form IC circuits each having a predetermined function, as well known. In two dimensions, IC circuit formation parts where the IC circuits are formed are placed like a matrix, dicing line parts are provided like a lattice surrounding the IC circuit formation parts, and the IC circuit formation parts are diced along the dicing line parts to form separate semiconductor devices (semiconductor chips) Then, often each semiconductor chip is mounted on connection pins of a lead frame, a film carrier, etc., and is sealed with a resin.
However, in recent years, attention has been focused on a method wherein connection pins are formed and sealing is executed before dicing for miniaturization and simplifying packaging. A chip size package (CSP) is available, for example, as described in JP-A-9-64049. FIG. 2 gives an outline of a chip size package 50 disclosed in JP-A-9-64049. A wafer 51 is formed with a desired element area, then is covered on a surface with a passivation film 52. An opening is made for exposing each metal electrode 53 (for example, a bonding pad) on the top layer and a rearrangement-rewiring layer 54 is formed by a Cu plating method so as to come in contact with the metal electrode 53 via the opening.
A metal post 55 is formed on the surface of the rearrangement-rewiring layer 54, the full face is coated with a seal resin 56, and the metal post 55 exposed from the seal resin 56 is formed with a solder bump or a solder ball 57.
In this state, dicing is performed along dicing line parts 58 to separate the wafer 51 into complete semiconductor chips 50.
However, the interfaces each between interlayer insulating films deposited in the semiconductor device are exposed to the flanks of the dicing lines. The interfaces become entry passages of moisture, causing malfunction of the IC circuit and destruction of the IC circuit.
Particularly, a number of interlayer insulating films such as a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film are provided depending on the number of layers of metal wiring and moreover each interlayer insulating film is formed by repeatedly depositing films each consisting of a plurality of layers, such as TEOS films or SOG films, considering distortion and flatness. The interfaces each between the films are exposed to the flanks formed in the dicing line parts, causing moisture resistance to be degraded.
It is therefore an object of the invention to provide a CSP improved in moisture resistance and high in reliability.
In a first aspect of the invention, a seal ring surrounding an IC circuit formation part formed on the main face of a semiconductor chip is placed between the IC circuit formation part and a dicing line part formed surrounding the IC circuit formation part.
Since a plug for cutting the interface between interlayer insulating films is provided as the seal ring, the passage of moisture is blocked.
In the first aspect, the dicing line part has a first dicing flank (side wall) which is an upper flank of the semiconductor chip covered with a resin and a second dicing flank comprising an exposed lower flank of the semiconductor chip.
If the upper flank reaches a semiconductor substrate, the interface between the interlayer insulating films above the semiconductor substrate is covered with the resin, thus double sealing structure can be made.
That is, the first aspect of the invention is characterized by the fact that in a semiconductor device of a chip size package structure having a size substantially equal to a size of one surface of a semiconductor substrate, the one surface of the semiconductor substrate being covered with a resin, a seal ring surrounding an IC circuit formation part formed on the main face of the semiconductor substrate is placed between the IC circuit formation part and a dicing line part formed surrounding the IC circuit formation part.
According to the configuration, the seal ring is provided on the outer periphery, thus if moisture is entered from the outside, it is blocked by means of the seal ring, making it possible to prevent the internal IC circuit formation part from being degraded.
In second and later aspects of the invention, the following advantages are provided in addition to the above-described advantage:
In a second aspect of the invention, in the semiconductor device, the seal ring may be formed so as to cover the outer peripheral ends of interlayer insulation films of at least two layers.
According to the configuration, since moisture is entered more easily from the edge of the interface, the end face is covered, whereby it is made possible to prevent entry of moisture.
In a third aspect of the invention, in the semiconductor device, the seal ring may be made up of seal grooves formed in the interlayer insulation films of at least two layers and seal material filled in the seal grooves.
In a fourth aspect of the invention, in the semiconductor device, the seal ring may be made up of a plurality of rings arranged in a periphery of the semiconductor substrate.
According to the configuration, moisture is blocked by means of a plurality of rings, so that it is made possible to block moisture perfectly.
In a fifth aspect of the invention, in the semiconductor device, the seal ring may be made up of a first layer ring and a second layer ring deposited on the first layer ring.
According to the configuration, the seal ring is made up of a plurality of layers, whereby it is made possible to form the seal ring at the same step as another functional circuit part; formation is more facilitated.
In a sixth aspect of the invention, in the semiconductor device, a pad formed so as to cover the cross sections of the first layer ring and the second layer ring may be placed between the first layer ring and the second layer ring.
According to the invention, if the seal ring is formed of a plurality of layers, sufficient sealing can also be provided. The pad is projected, whereby the moisture entry passage can be lengthened and it is made possible to better block moisture.
In a seventh aspect of the invention, in the semiconductor device, the first layer ring, the second layer ring, and the pad may be formed of metal material.
In an eighth aspect of the invention, in the semiconductor device, the first layer ring, the second layer ring, and the pad may be formed at the same step as the IC circuit formation part.
According to the configuration, they can be formed without adding a special step; manufacturing is facilitated.
In a ninth aspect of the invention, in the semiconductor device, the seal material may be metal barrier layers formed so as to cover the inner walls of the seal grooves and metal layers filled in the metal barrier layers.
According to the configuration, it is made possible to block moisture more reliably.
In a tenth aspect of the invention, in the semiconductor device, the metal barrier layers may be made of Ti or TiN and the metal layers may be made of tungsten or copper.
In an eleventh aspect of the invention, in the semiconductor device, the seal material may contain a hygroscopic material.
According to the configuration, if moisture is entered from the outside, it is absorbed in the hygroscopic material and it is made possible to prevent moisture from arriving at the internal IC circuit part.
In a twelfth aspect of the invention, in the semiconductor device, the seal material may be an insulating material.
In a thirteenth aspect of the invention, in the semiconductor device, the seal material may be a silicon nitride film formed so as to cover the inner walls of the seal grooves and a silicon oxide film filled in the seal grooves coated with the silicon nitride film.
In a fourteenth aspect of the invention, in the semiconductor device, the dicing line part may have a first dicing flank covering an upper flank of a semiconductor chip with the resin and a second dicing flank to which a lower flank of the semiconductor chip is exposed.
According to the configuration, the outermost periphery is coated with resin and it is made possible to block moisture more reliably.
In a fifteenth aspect of the invention, in the semiconductor device, the interface between the first dicing flank and the second dicing flank may be formed so as to become a predetermined depth position from the surface level of the semiconductor substrate.
In a sixteenth aspect of the invention, the semiconductor device may further include a spacer formed so as to surround said seal ring and cover an end part of an interface between an interlayer insulating film and another layer at the dicing line part.
According to the configuration, moisture is also blocked by the spacer, so that it is blocked more reliably.
In a seventeenth aspect of the invention, in the semiconductor device, the spacer may be placed away from the seal ring.
According to an eighteenth aspect of the invention, there is provided a semiconductor substrate of chip size package structure having a size substantially equal to a size of one surface of a semiconductor substrate, the one surface of the semiconductor substrate being covered with a resin, the chip size package comprising a spacer formed so as to surround an IC circuit formation part formed on the main face of the semiconductor substrate and cover an end part of the interface between an interlayer insulating film and another layer at a dicing line part.
According to the configuration, moisture can be blocked by the spacer, and it is made possible to improve the reliability of the semiconductor device.
In a nineteenth aspect of the invention, in the semiconductor device, the dicing line part may have a first dicing flank covering an upper flank of a semiconductor chip and a second dicing flank to which a lower flank of the semiconductor chip is exposed.
In a twentieth aspect of the invention, in the semiconductor device, the interface between the first dicing flank and the second dicing flank may be formed so as to become a predetermined depth position from the surface level of the semiconductor substrate.
According to the invention, the IC circuit formation part easily affected by moisture is completely covered, so that it is made possible to block moisture more reliably.